The present invention relates to transmitting equipment and receiving equipment, and particularly to transmitting and receiving equipment with multiple-speed conversion process by means of asynchronous mapping to a high-order transmission frame in an optical signal transmission system.
In the long-distance optical signal transmission system using optical fibers, a reduction in network cost is achieved by extending the transmission distance while ensuring the transmission quality through mapping to a high-order transmission frame added with an FEC (Forward Error Correction) code defined in ITU-T G. 709. Further the usability of the line is improved by increasing the transmission capacity per line, and now a transmission speed of 10 Gbits/s per line is generally used. For example, low order group signals represented by those of 2.4 Gbits/s, which are used in existing networks, are transmitted in such a way that a plurality of lines are multiplexed and accommodated in a signal of 10 Gbits/s, and then mapped to the high-order transmission frame.
Meanwhile in the long-distance optical signal transmission system that accommodates existing network lines, there is a demand for ensuring the so called transparency in order to make it possible to accommodate various types of lines without any influence on the network management and clock network synchronization system of the existing network. More specifically, the transmitting equipment multiplexes transmission signals of the existing network (hereinafter referred to as client signals) without rewriting the terminals and OHs (Over Heads) and maps to the high-order transmission frame, and the receiving equipment reproduces the client signals from the high-order transmission frame without rewriting the terminals and OHs, respectively. Particularly when different existing networks supply client signals whose clocks are not synchronized with each other, it is necessary to multiplex a plurality of client signals having frequency deviation in their clock frequencies, before mapping the client signals to the high-order transmission frame. Thus asynchronous mapping by stuffing multiplexing is generally needed. In ITU-T G.709, there are defined various asynchronous mapping methods of client signals, clock frequency deviations of client signals that can be accommodated, and ranges of stuffing rate.
The long-distance optical transmission system will be described with reference to FIGS. 1 and 2. Here FIGS. 1 and 2 are block diagrams of different long-distance optical transmission systems.
In FIG. 1, a long-distance optical transmission system 1000A includes an optical multiplex transmitting equipment 10-1, transponders 20, and an optical multiplex transmitting equipment 10-2. The optical multiplex transmitting equipment 10 includes: multiplexing equipment 40 for multiplexing four client signals of 2.5 Gbits/s to a high-order signal of 10 Gbits/s; and demultiplexing equipment 50 for converting the high-order signal of 10 Gbits/s to four client signals of 2.4 Gbits/s. Further the transponder 20 includes optical amplifiers 30-1, 30-2, or optical amplifiers 30-3, 30-4. The optical amplifier 30 amplifies the optical signal as it is. Here, the distance between the optical multiplex transmitting equipment 10-1 and the optical multiplex transmitting equipment 10-2 is a high-order transmission frame section. The maximum distance between the optical multiplex transmitting equipment 10 and the transponder 20 is 80 km. The maximum distance between the optical multiplex transmitters 10 is 240 km. It is possible to add an FEC code to the high-order signal of 10 Gbits/s.
In FIG. 2, an optical transmission system 1000B includes an optical transmitting equipment 60-1, transponders 20, and an optical transmitting equipment 60-2. The configuration of the transponders 20 between the optical transmitters 60 is the same as in FIG. 1. However, transmitting equipment 70 of the optical transmitting equipment 60 adds the FEC code to an optical signal of 10 Gbits/s which is a client signal, and then receiving equipment 80 of the optical transmitting equipment 60 receives the optical signal through the high-order transmission frame section which is a long distance section. The client signal shown in FIG. 2, which is the optical signal of 10 Gbits/s, is added with an FEC signal of about 7% and is transmitted over the high-order transmission frame section.
With respect to the configuration of the related art that performs the multiple-speed conversion process by means of asynchronous mapping to the high-order transmission frame in the optical signal transmission system, there is known a method, for example, described in JP-A No. 289326/2004. The configuration of equipment on the transmitting side according to JP-A 289326/2004 will be described with reference to FIG. 3. Here FIG. 3 is a block diagram of transmitting equipment in the related art.
In FIG. 3, a client signal input as an optical signal of 2.5 Gbits/s is subjected to clock extraction and data reproduction by a CDR (Clock Data Recovery) 101. The extracted clock is frequency divided by a frequency divider 104 to a slower speed that can be processed in the transmitting equipment. The reproduced data is serial to parallel converted by an S/P (Serial/Parallel) 102. The serial-parallel converted data is written to a FIFO memory 106 according to an address value that is instructed by a write address counter 105 and generated by the slow clock from the frequency divider 104.
The high-order transmission frame, which is a frame signal added with FEC, is generated in a high-order frame generator 107. The client signal to be stored in the high-order transmission frame is read out to the high-order frame generator 107 from the FIFO memory 106, according to an address value instructed by a read address counter 108 operated by a reference clock that is supplied from an oscillator (hereinafter abbreviated to OSC) 111 into the transmitting equipment.
The reference clock, which is generated by the OSC 111 and supplied into the transmitting equipment, is not synchronous with the extracted clock of the client signal in master-slave configuration. When there is a frequency deviation in the clock frequencies, a difference occurs between the data writing speed of the client signal from the S/P 102 to the FIFO memory 106 and the data reading speed of the client signal from the FIFO memory 106 to the high-order frame generator 107. Thus stuffing is necessary as a method of asynchronous mapping to absorb the speed difference. The stuffing method includes: positive stuffing (PJ: Positive Justification) for equally delaying the data transfer speed of the client signal by temporarily stopping reading of the client signal from the FIFO memory 106 to the high-order frame generator 107 and by inserting dummy data instead; and negative stuffing (NJ: Negative Justification) for equally accelerating the data transfer speed of the client signal by adding reading of the client signal from the FIFO memory 106 to the high-order frame generator 107 and by inserting a client signal into the OH of the high-order frame. In the present specification, the positive stuffing insertion and the negative stuffing insertion are collectively referred to as stuffing insertion.
An address monitor 109 calculates the remaining amount of data of the client signal in the FIFO memory 106 by comparing the address values of the write address counter 105 and the read address counter 108. Then a stuff determination circuit 110 determines the necessity of the stuffing insertion to the high-order transmission frame. For example, when the data reading speed of the client signal from the FIFO memory 106 to the high-order frame generator 107 is faster than the data writing speed of the client signal from the S/P 102 to the FIFO memory 106 with reduced amount of unread data of the client signal in the FIFO memory 106, the stuff determination circuit 110 notifies the read address counter 108 and the high-order frame generator 107 to perform the positive stuffing. On the other hand, when the data reading speed of the client signal from the FIFO memory 106 to the high-order frame generator 107 is slower than the data writing speed of the client signal from the S/P 102 to the FIFO memory 106 with increased amount of unread data of the client signal in the FIFO memory 106, the stuff determination circuit 110 notifies the read address counter 108 and the high-order frame generator 107 to perform the negative stuffing. The high-order frame generator 107 performs a stuffing operation in response to a stuffing operation request from the stuff determination circuit 110, generating a high-order frame together with stuffing information, OH of the high-order transmission frame, and an error correction check bit. The high-order transmission frame is serial to parallel converted by the P/S (Parallel/Serial) 113 and is transmitted as an optical signal to the next stage receiving equipment.
The above described stuffing operation is repeated to control that the data writing speed of the client signal from the S/P 102 to the FIFO memory 106 is identical to the data reading speed of the client signal from the FIFO memory 106 to the high-order frame generator 107 on a time average basis. Thus it is possible to perform the speed conversion process in the transmitting equipment, even if the reference clock in the transmitting equipment and the extracted clock of the client signal are not synchronous in master-slave configuration.
Next, FIG. 4 shows an example of the configuration of equipment on the receiving side according to the related art. Here FIG. 4 is a block diagram of receiving equipment in the related art.
The high-order transmission frame input as an optical signal from a transmission line is subjected to clock extraction and data reproduction by a CDR 201. The extracted clock is frequency divided by a frequency divider 204 to a slower speed that can to be processed in the receiving equipment. The reproduced data is serial to parallel converted by an S/P 202. The serial-parallel converted data is terminated by a high-order frame terminator 203. Then stuffing information notified from the other equipment is output to a stuff detector 205. Based on the received stuffing information, when receiving positive stuffing, the stuff detector 205 performs a de-stuffing operation to temporarily stop a write address counter 206 so that the dummy data inserted by the other equipment is not written to a FIFO memory 207. When receiving negative stuffing, the stuff detector 205 de-stuffs the write address counter 206 so that the client signal additionally inserted to the OH of the high-order transmission frame by the other equipment is written to the FIFO memory 207. The client signal extracted from the high-order frame terminator 203 is written to the FIFO memory 207 according to an address value instructed by the write address counter 206, based on a slow clock from the frequency divider 204 and on the information from the stuff detector 205.
With the operation described above, the client signal mapped to the received high-order transmission frame is de-stuffed without missing data and entirely stored in the FIFO memory 207.
A clock for operating a read address counter 209 of the FIFO memory 207 is supplied from a voltage controlled crystal oscillator (hereinafter abbreviated to VCXO) 212. The VCXO 212 is configured as a PLL (Phase Locked Loop) controlled by a phase comparison result from a phase comparator (hereinafter abbreviated to PC) 210. The VCXO 212 is controlled so that the phase difference of the PC 210 is zero through a filter part 211 that determines the control characteristics of the PLL. The PC 210 calculates the amount of data remaining in the FIFO memory 207 by comparing the address values of the write address counter 206 and read address counter 207 of the FIFO memory 207. For example, when the data writing speed of the client signal from the high-order frame terminator 203 to the FIFO memory 207 is faster than the data reading speed of the client signal from the FIFO memory 207 to the P/S 214 with increased amount of unread data of the client signal in the FIFO memory 207, the PC 210 increases the clock frequency of the output of the VCXO 212 and thus controls the PLL to increase the data reading speed of the client signal from the FIFO memory 207 to the P/S 214. On the other hand, when the data writing speed of the client signal from the high-order frame terminator 203 to the FIFO memory 207 is slower than the data reading speed of the client signal from the FIFO memory 207 to the P/S 214 with reduced amount of unread data of the client signal in the FIFO memory 207, the PC 210 reduces the clock frequency of the output of the VCXO 212 and thus controls the PLL to reduce the data reading speed of the client signal from the FIFO memory 207 to the P/S 214. The client signal read from the FIFO memory 207 is serial to parallel converted by the P/S 214 and is transmitted as an optical signal to the next stage optical transmission system.
According to the above described related art, the transmitting equipment maps the client signal asynchronously to the high-order transmission frame, by comparing the address values of the write address counter and read address counter of the FIFO memory in which the client signal is stored and by performing the stuffing operation so that the data writing speed and data reading speed of the client signal are identical on a time average basis, without synchronizing with the clock extracted from the client signal in master/slave configuration. The receiving equipment reproduces in the output the same clock frequency as the client signal input to the transmitting equipment, by comparing the address values of the write address counter and read address counter of the FIFO memory in which the client signal is stored and by performing the de-stuffing operation so that the data writing speed and data reading speed of the client signal are identical on a time average basis. Thus the receiving equipment can transmit the client signal mapped to the high-order transmission frame without missing data, to the next stage optical transmission system.
Next, a description will be made with respect to jitter and wonder generated by the stuffing operation with reference to FIGS. 5 to 7. Here FIG. 5 is a view illustrating the variation in phase difference over time. FIG. 6 is a view illustrating the transfer characteristic of PLL in receiving equipment. FIG. 7 is a view illustrating the phase difference correction by reduction of stuff determination threshold.
In the transmitting equipment, as the extracted clock of the client signal and the reference clock supplied from the OSC 111 are asynchronous with each other, the clock phases are gradually displaced when there is a frequency deviation in these clock frequencies. In the above described related art, the phase difference is detected by comparing the address values of the write address counter 105 and read address counter 108 of the FIFO memory 106 and by calculating the amount of unread data of the client signal in the FIFO memory 106. When the phase difference exceeds a certain determination threshold, the phase difference between the clock frequencies is corrected to be constant on a time average basis by performing a stuffing insertion by the positive or negative stuffing.
FIG. 5 shows the manner in which the phase difference is corrected by the positive stuffing. In FIG. 5, there is shown the variation of the phase difference that remains without being completely corrected within a range of the stuff determination threshold. This variation is jitter or wonder generated by the stuffing operation. The peak amount of the jitter or wonder generated by the stuffing operation is substantially the same value as the determination threshold of the stuffing operation. The frequency of the jitter or wonder generated by the stuffing operation is dependent on the frequency deviation between the clock frequencies. The frequency of the jitter or wonder increases when the frequency deviation is large, and the frequency of the jitter or wonder decreases when the frequency deviation is small. Incidentally in ITU-T G.810, the jitter is defined as phase variation at rates greater than 10 Hz while the wonder is defined as phase variation at rates less than 10 Hz.
As described above, the receiving equipment includes the PLL for controlling the clock frequency of the output of the VCXO 212 based on the amount of unread data of the client signal in the FIFO memory 207. The input/output transfer characteristic of the PLL are generally designed to have LPF (Low Pass Filter) characteristics as shown in FIG. 6. With the LPF characteristics, when a frequency fo of the jitter or wonder generated by the stuffing operation in the transmitting equipment is sufficiently higher than a cut-off frequency fc of the PLL in the receiving equipment, the jitter or wonder of the clock of the client signal reproduced in the receiving equipment is suppressed sufficiently to some extent. However, when the frequency fo of the jitter or wonder generated by the stuffing operation in the transmitting equipment decreases, the jitter or wonder is not suppressed even by the LPF characteristics of the PLL of the receiving equipment. As a result, the jitter or wonder is output being superimposed on the reproduced clock of the client signal. Reduction of the cut-off frequency of the PLL is effective to suppress the jitter or wonder generated by the stuffing operation. However, when the cut-off frequency of the PLL is reduced, the following problems generally arise: the response of the PLL is delayed, the pull-in time increases, and the peak is likely occur in the input/output transfer characteristic of the PLL. In fact, sufficient suppress characteristics are not often realized.
In order to suppress the jitter or wonder generated when the client signal is reproduced by the stuffing operation, it is the most important to reduce the insertion amount per stuffing operation by detecting the phase difference between the extracted clock of the client signal and the reference clock with high accuracy, and thereby reducing the stuff determination threshold as small as possible, in other words to reduce the peak amount of the jitter or wonder generated by the stuffing operation. FIG. 7 shows the manner in which the phase difference is corrected by the positive stuffing when the stuff determination threshold is reduced. Comparing with FIG. 5, when the stuff determination threshold is reduced, the peak amount of the jitter or wonder generated by the stuffing operation becomes smaller, while the frequency of the jitter or wonder generated by the stuffing operation becomes relatively high as the number of times of stuffing insertion increases. Thus the jitter or wonder can be more effectively suppressed by the PLL of the receiving equipment.
As a technology focusing on the above described feature to suppress the jitter, there has been proposed a method described in JP-A No. 282632/2004. According to JP-A No. 282632/2004, the stuff determination is made by comparing the address values of the write address counter 105 and read address counter 108 of the FIFO memory 106. Generally the stuff determination threshold is limited by the slow clock frequency which is the data writing clock and data reading clock of the client signal to/from the FIFO memory 106, and the insertion amount per stuffing operation ranges from one byte to several bytes. In order to prevent such a problem, the transmitting equipment performs bit stuffing insertion at a timing separated in an average manner according to the stuff generation interval. Then the receiving equipment reproduces the client signal based on the bit stuffing information inserted in an average manner. As a result, it is possible to suppress the jitter by reducing the insertion amount per stuffing operation.
However, the above described related art has the following problems.
First, the stuff determination threshold is limited by the slow clock frequency of the FIFO memory as the stuff determination is made by comparing the address values of the read address counter and write address counter of the FIFO memory. The slow clock frequency is used in such elements as the client signal and the high-order terminator that have a relatively large scale of logics. Generally in order to satisfy the timing of such logical circuits, the clock frequency is frequency divided to a speed as slow as about 100 MHz. There is no solution presented for the fundamental problem with respect to reducing the stuff determination threshold in JP-A No. 289326/2004.
Second, in JP-A No. 282632/2004, there is proposed the method to solve the first problem in a pseudo manner, in which the stuffing information of several bytes detected at a time is separated on a time average basis to perform as bit stuffing. However, the phase difference between the client signal and the client signal mapped to the high-order transmission frame is not detected with high accuracy. Thus, although the jitter which is the phase variation of a relatively high frequency can be suppressed, there is a problem for the wonder which is the phase variation of a very low frequency in which the stuffing information is rarely detected. That is, it is difficult to perform the bit stuffing correctly separated on a time average basis, as the time interval of when the next stuffing information is generated, or the stuffing interval, may not be expected. Thus there has been a problem that the wonder is not suppressed and remains in the reproduced clock of the client signal in the output of the receiving equipment.
Third, in the above described related art, as the stuff determination is made by comparing the address values of the read address counter and write address counter of the FIFO memory, the stuff determination can be made only between the read address counter and write address counter of the FIFO memory that performs asynchronous mapping. Because of this problem, for example, when the PLL is used for phase adjustment of the internal logic and the like with respect to the clock supplied to the read address counter, or when the PLL is used as means of generating a multiplied clock to form an intermediate transmission frame through which the client signal is multiplexed and mapped to the high-order transmission frame, jitter or wonder generated by the PLL is added to the clock that operates the read address counter. For this reason, an accurate stuff determination may not be made by comparing the read address counter and write address counter of the FIFO memory. Thus there has been a problem that in the other receiving equipment, the jitter or wonder generated by the PLL is not perfectly suppressed and remains in the reproduced clock of the client signal.